Special Topic – January 2026

Breaking the Memory Wall

Beyond the GPU: The Hidden Bottleneck

While the broader consensus remains fixated on the "brains" of Artificial Intelligence (the GPUs from Nvidia), this month’s Investment Committee featured a special deep dive into the "plumbing" required to make those brains function.

We looked past the processors to identify a critical, often misunderstood constraint in the AI ecosystem: the Memory Wall.

The central thesis is simple but profound: A GPU is only as fast as the data fed into it. You can build a Ferrari engine (the Nvidia Blackwell or Rubin chips), but if you fuel it with a garden hose (standard memory), that engine sits idling. Currently, AI infrastructure is facing a "garden hose" crisis, and the solution—High Bandwidth Memory (HBM)—is creating a structural investment opportunity that the market is still mispricing.

The Physics of HBM: Why This Time Is Different

To understand the investment case, one must understand the architecture. Traditional memory (DDR) is "planar"—chips sit side-by-side on a board. This works for laptops but fails for AI models that require massive data throughput for training and inference.

The industry’s solution is HBM. Instead of sitting side-by-side, memory chips are stacked vertically (like floors in a skyscraper) and placed directly next to the GPU on a silicon "interposer." This architecture solves the speed problem but introduces a massive manufacturing headache known as Yield.

In a traditional setup, if one memory chip fails, you replace it. In an HBM stack of 8, 12, or 16 layers, if one layer fails, the entire stack is discarded. This complexity acts as a natural barrier to entry. It is not enough to have capital; you must have the engineering precision to achieve viable yields.

The "Cyclical" Trap

The market is currently pricing memory manufacturers (the "Big Three": SK Hynix, Samsung, Micron) as cyclical plays—expecting a boom followed by a bust, similar to the smartphone cycles of the past.

We believe this is a fundamental category error. We are witnessing a shift from cyclical to structural:

• Insatiable Demand: Hyperscalers (Meta, Google, Microsoft) have committed billions to AI capex. The demand for HBM is projected to outstrip supply by roughly 20-30 million gigabytes in 2026.

  
  

• Capacity Cannibalization: To make HBM, manufacturers must repurpose production lines that used to make standard DDR memory. This restricts the supply of standard memory, putting a floor under prices across the entire sector—even for legacy tech.

  
  

• The Packaging Bottleneck: Even if memory makers could produce infinite chips, the industry is limited by advanced packaging capacity (specifically the "interposer" layer), a constraint that will take 18-24 months to fully resolve.

The Landscape: The Big Three

Our analysis highlights the distinct positioning of the three dominant players:

1. SK Hynix (The Leader): Currently the "king" of HBM, holding ~60% market share and serving as the primary partner for Nvidia. They have solved the yield puzzle better than anyone else, commanding a premium valuation.

   
   

2. Samsung (The Catch-Up Play): Despite being the largest memory maker by volume, Samsung has struggled with yield and certification. However, they are aggressively pivoting capacity to catch up, making them a high-beta option for when certification is achieved.

   
   

3. Micron (The Geopolitical Hedge): As the primary US-based manufacturer, Micron benefits from the CHIPS Act and the desire for supply chain security. They are rapidly gaining share (from 4% to ~21%) and are effectively sold out for the coming year.

Conclusion

The "Memory Wall" is not a technical glitch; it is the defining economic constraint of the next phase of AI. Until the physics of memory catch up to the speed of processors, pricing power will remain firmly with the manufacturers who can deliver high-yield stacks.

Authors: George Fatouros PhD, Special Guest